Free Software Radio
A Rose by Any Other Name Would Run Just as Long
Understanding Computational and Hardware Complexity in Software Defined Radio Framework
Abstract: Radio based communication systems and imagers operate under real-time constraints. Off-loading computes to an FPGA seems like a solution to speeding-up your application but comes with many pitfalls.
Specifically, software-oriented implementations fail to achieve the required interface bandwidths or computational throughput required to see a speed-up.
In this talk, we will discuss the organization of common compute motif's in software-defined-radio and their complexity in time and resources for FPGAs.
Rough goals of talk:
1) Communicate why FPGA acceleration would be attractive
2) Discuss common pitfalls
2a) A behaviorally oriented accelerator
2b) Starving the beast, failing to provide the required data bandwidths
2c) Processor oriented runtime, creates execution overheads
3) Thinking about accelerators, what do they look like
3a) FFT
3b) Correlators
3c) Matrix-Vector Multiply
4) Building an off-load model
Additional information
| Type | devroom |
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