Hardware & Making
Open CPU / SoC design, all the way up to Debian
This lecture will cover many aspect of designing a RISC-V CPU, out-of-order execution, multi-core, memory coherency, security and running linux and debian on a FPGA.
This will be based on the recently developped NaxRiscv core, a free and opensource RISC-V softcore. I will cover many interresting aspect of the project/flow to provide a large overview of all the different technical aspect in such project.
Additional information
| Live Stream | https://streaming.media.ccc.de/37c3/zuse |
|---|---|
| Type | lecture |
| Language | English |
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