Hardware & Making

Demystifying Common Microcontroller Debug Protocols

Saal GLITCH
Sean "xobs" Cross
Many developers know that the answer to "How do I debug this microcontroller" is either "JTAG" or "SWD". But what does that mean, exactly? How do you get from "Wiggling wires" to "Programming a chip" and "Halting on breakpoints"? This talk will cover how common debug protocols work starting from signals on physical wires, cover common mechanisms for managing embedded processors, and ending up at talking to various common microcontrollers.
Embedded programming is the art of shrinking complex programs in tiny packages by throwing away unnecessary features. With modern microcontrollers, debugging need not be one of the features thrown away. Most modern chips include some form of low-level access, but the technical details aren't widely understood. Many users of embedded firmware will use their preferred debugger without thinking too hard about what's going on underneath. We'll start by covering what it means to debug embedded software. The primitives required to have an interactive debug session are surprisingly minimal. From this, we'll build up a list of requirements and "nice to haves" to make a debugging environment comfortable, and reference existing "bespoke" debug approaches. We'll cover several examples of debug engines ranging from cores designed to go into FPGAs to tiny 8-bit microcontrollers. Next, we'll take a step back and describe the common lower-level protocols such as JTAG and SWD. These describe physical signals that go between the host and the target. We'll compare various protocols and see how they map onto the higher-level primitives discussed earlier. Armed with examples, we'll see how the protocol stack is formed. Next, we'll use the knowledge of low-level protocol implementations and the requirements for debugging to look at common abstractions on top of physical transports to implement core control. This will bridge the gap between "JTAG or SWD are the protocol" to "Poking a value in memory on a microcontroller". In this section, we'll cover the more common and generic uses such as Arm's ADI and the RISC-V DMI and see how complex and cross-target configurations are built to be rigid enough to have rich debug features while flexible enough to handle a wide range of processor configurations. Finally, we'll cover common tasks such as programming flash memory, watchpoints, and single-step debugging -- things that we take for granted in the desktop world and would like to have when programming for a potato that costs less than an actual potato.

Additional information

Live Stream https://streaming.media.ccc.de/38c3/glitch
Type Talk
Language English

More sessions

12/27/24
Hardware & Making
DorotaC
Saal GLITCH
I'm not big-brained enough to use cameras on Linux, so I decided to write my own camera stack (based on a real story).
12/27/24
Hardware & Making
Saal 1
Reverse engineering the Wi-Fi peripheral of the ESP32 to build an open source Wi-Fi stack.
12/27/24
Hardware & Making
Saal 1
The Iridium satellite (phone) network is evolving and so is our understanding of it. Hardware and software tools have improved massively since our last update at 32C3. New services have been discovered and analyzed. Let's dive into the technical details of having a lot of fun with listening to satellites.
12/27/24
Hardware & Making
Saal GLITCH
The 530 tons and 63 meter tall Ariane 6 rocket finally launched on July 9th 2024 carrying our open-source developed payloads – the SIDLOC experiment and the satellite Curium One – into space. SIDLOC tested a new, open, low-power standard for identifying and precisely locating spacecraft whilst our satellite Curium One established an open-source baseline for larger CubeSat systems and allowed us to test a bunch of new technologies. From sourcing a launch opportunity to the final integration ...
12/27/24
Hardware & Making
Thorsten Hellert
Saal ZIGZAG
Recent breakthroughs in machine learning have dramatically heightened the demand for cutting-edge computing chips, driving advancements in semiconductor technologies. At the forefront of this progress is Extreme Ultraviolet (EUV) lithography—a transformative method in microchip fabrication that enables the creation of ultra-small, high-performance devices. However, the path from raw materials to these state-of-the-art chips navigates a complex global supply chain riddled with technical ...
12/27/24
Hardware & Making
giulioz
Saal GLITCH
Custom silicon chips are black boxes that hold many secrets, like internal ROMs, security features and audio DSP algorithms. How does one start reverse engineer them? Let's look at the basics of silicon reverse engineering, what gate array chips are, and how some tooling can generate Verilog code automatically from a die shot.
12/27/24
Hardware & Making
Andrew 'bunnie' Huang
Saal GLITCH
IRIS (Infra-Red, *in situ*) is a technique for non-destructively inspecting the construction of a select but common type of chip. It can improve visibility into our hardware and provide supporting evidence of its correct construction, without desoldering chips or expensive analytical gear. This talk covers the theory behind IRIS, as well as some embodiments of the technique. I will also frame the relevance of IRIS in the face of various threat scenarios. Time permitting, I’ll also show how you ...