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VERSION:2.0
PRODID:calendify.com
BEGIN:VEVENT
UID:calendify-session-eLYOwaB8gzp
DTSTART:20161228T161500Z
SEQUENCE:0
TRANSP:OPAQUE
DTEND:20161228T171500Z
URL:https://calendify.com/session/eLYOwaB8gzp
LOCATION:Saal 6
SUMMARY:Formal Verification of Verilog HDL with Yosys-SMTBMC
CLASS:PUBLIC
DESCRIPTION:https://calendify.com/session/eLYOwaB8gzp
DTSTAMP:20260417T100209Z
CREATED:20220415T135303Z
LAST-MODIFIED:20220415T135303Z
END:VEVENT
END:VCALENDAR