Libre-Open VLSI and FPGA

corundum

From a NIC to a Platform for In-Network Compute
D.open-hardware
<p>The talk provides an introduction to the corundum project, implementing a 100 GbE NIC based on Commercial-off-the-shelf (COTS) FPGA cards, e.g. Xilinx Alveo Cards. The project consists of all necessary RTL components, e.g. PCIe DMA engine, NIC datapath, MAC, PHY and integration of vendor specific IP cores, such as transceivers and PCIe hard-IP cores. In combination with the provided driver and debugging utility the ready-to-experiment state just requires a supported FPGA card + compiler to kick-off playing with the project.</p> <p>The existing state provides the platform for future In-Network Compute platform research, allowing for application logic to be balanced across hardware acceleration and software flexibility. The platform uniquely allows for experiments with lower layer protocols, e.g. PHY layer coding.</p> <p>The talk concludes with an overview about short term and mid term goals of the project.</p>

Additional information

Type devroom

More sessions

2/6/22
Libre-Open VLSI and FPGA
Jean-Paul Chaput
D.open-hardware
<p>Sorbonne Université, in collaboration with Chips4Makers and LibreSOC are working to provide a complete FOSS toolchain to make ASICs in mature technological nodes, that is, no smaller than 130nm. We take a circuit description in HDL, synthetize with Yosys but instead of targetting a FPGA, use an ASIC standard cell library to get the RTL description. From there, with Coriolis2, we perform the classical steps of a RTL to GDSII flow, that is, placement, routage along with very basic timing ...
2/6/22
Libre-Open VLSI and FPGA
Yimin Gu
D.open-hardware
<p>Both software-defined radio and FPGA are interesting. Especially, the combination of AD936X RF transceiver and ZYNQ 7020 level FPGA SoC is capable of running openwifi. Price has been keeping average DIYers away from this kind of platform as evaluation boards from ADI and Xilinx are both extremely expensive. Cheaper ones like ANTSDR exist, but seems all of them have tied the RF and ZYNQ chip together, so these are not suitable for generic ZYNQ development anymore.</p> <p>In this talk, I want ...
2/6/22
Libre-Open VLSI and FPGA
Cesar Strauss
D.open-hardware
<p>GTKWave is a nice tool for displaying signal traces, while developing with Hardware Description Languages, and has many formatting features like changing signal color, grouping signals in a hierarchy, etc. However, it can become tedious to manually edit through the GUI. Also, its document format, while ASCII, is a bit cryptic, and contains extra information pertaining to the GUI (window and panel sizes, last modification date, etc.), making it inconvenient for placing in revision control.</p> ...
2/6/22
Libre-Open VLSI and FPGA
Luke Kenneth Casson Leighton
D.open-hardware
<p>nmigen™ is a tool for creating hardware, whether for ASICs or for FPGAs. it is not itself an actual language (like Verilog or VHDL), and it is not like MyHDL which allows translation of a limited subset of python source code into verilog. Instead, nmigen allows you - in python - to create HDL constructs, and to mix those in with the full power of python OO techniques: objects, classes, even multiple inheritance, which is sorely lacking in the Hardware world.</p> <p>this talk will go through ...
2/6/22
Libre-Open VLSI and FPGA
Mohamed Kassem
D.open-hardware
<p>This presentation by Mohammed Kaseem, the CTO of e-Fabless, will outline how e-Fabless is empowering Libre/Open VLSI Hardware development. There are two initiatives: ChipIgnite which provides significantly-reduced cost Shuttle runs, and the Google-sponsored Skywater 130nm Programme.</p>
2/6/22
Libre-Open VLSI and FPGA
David Lanzendörfer
D.open-hardware
<ul> <li>An overview of the minimal process flow</li> <li>Talking about ways to implement it in a garage/shipping container environment.</li> </ul>