RISC-V

Building Loosely-coupled RISC-V Accelerators

Using Chisel/FIRRTL to build accelerator templates and collateral for the ESP SoC platform
K.3.401
Schuyler Eldridge
The burgeoning RISC-V hardware ecosystem includes a number of microprocessor implementations [1, 3] and SoC generation frameworks [1, 2, 7]. However, while accelerator “sockets” have been defined and used (e.g., Rocket Chip’s custom coprocessor/RoCC), accelerators require additional collateral to be generated like structured metadata descriptions, hardware wrappers, and device drivers. Requiring manual effort to generate this collateral proves both time consuming and error prone and is at odds with an agile approach to hardware design. However, the existence and use of hardware construction languages and hardware compilers provides a means to automate this process. Through the use of the Chisel hardware description language [4] and the FIRRTL hardware compiler [5], we provide a definition of an abstract accelerator template which users then implement to integrate an accelerator with the Embedded Scalable Platform (ESP) System-on-Chip platform [2, 8]. Through the use of this template, we are able to automatically generate XML metadata necessary to integrate accelerators with the ESP platform and work on generating all collateral is in progress. Our accelerator template is open source software provided under an Apache 2.0 license [6]. [1] CHIPS alliance Rocket-chip. GitHub Repository. Online: https://github.com/chipsalliance/rocket-chpi. [2] Columbia University Embedded scalable platform. git repository. Online: https://github.com/sld-columbia/esp. [3] ETH Zurich Ariane. GitHub Repository. Online: https://github.com/pulp-platform/ariane. [4] Freechips Project Chisel3. GitHub Repository. Online: https://github.com/freechipsproject/chisel3. [5] Freechips Project FIRRTL. GitHub Repository. Online: https://github.com/freechipsproject/firrtl. [6] IBM ESP chisel acclerators. GitHub Repository. Online: https://github.com/ibm/esp-chisel-accelerators. [7] Princeton University OpenPiton. GitHub Repository. Online: https://github.com/PrincetonUniversity/openpiton. [8] ESP: The open-source heterogeneous system-on-chip platform. Online: https://www.esp.cs.columbia.edu/.

Additional information

Type devroom

More sessions

2/1/20
RISC-V
Greg Chadwick
K.3.401
Ibex implements RISC-V 32-bit I/E MC M-Mode, U-Mode and PMP. It uses an in order 2 stage pipe and is best suited for area and power sensitive rather than high performance applications. However there is scope for meaningful performance gains without major impact to power or area. This talk describes work done at lowRISC to analyse and improve the performance of Ibex. The RTL of an Ibex system is simulated using Verilator to run CoreMark and Embench and the traces analysed to identify the major ...
2/1/20
RISC-V
Dan Petrisko
K.3.401
BlackParrot is a Linux-capable, cache-coherent RISC-V multicore, designed for efficiency and ease of use. In this talk, we will provide an architectural overview of BlackParrot, focusing on the design principles and development process as well as the software and hardware ecosystems surrounding the core. We will also discuss the project roadmap and our plans to engage the open-source community. Last, we will demonstrate a multithreaded RISC-V program running on top of Linux on a multicore ...
2/1/20
RISC-V
K.3.401
HammerBlade is an open source RISC-V manycore that has been under development since 2015 and has already been silicon validated with a 511-core chip in 16nm TSMC. It features extensions to the RISC-V ISA that target GPU-competitive performance for parallel programs (i.e. GPGPU) including graphs and ML workloads. In this talk we will overview the components of the HW and software ecosystem in the latest version, and show you how to get up and running as an open source user or contributor in ...
2/1/20
RISC-V
K.3.401
ESP is an open-source research platform for RISC-V systems-on-chip that integrate many hardware accelerators. ESP provides a vertically integrated design flow from software development and hardware integration to full-system prototyping on FPGA. For application developers, ESP offers domain-specific automated solutions to synthesize new accelerators for their software and map it onto the heterogeneous SoC architecture. For hardware engineers, ESP offers automated solutions to integrate their ...
2/1/20
RISC-V
Karthik Swaminathan
K.3.401
RISC-V processors have gained acceptance across a wide range of computing domains, from IoT to embedded/mobile class and even in server-class processing systems. In processing systems ranging from connected cars and autonomous vehicles, to those on-board satellites and spacecrafts, these processors are targeted to function in safety-critical systems, where Reliability, Availability and Serviceability (RAS)-based considerations are of paramount importance. Along with potential system ...
2/1/20
RISC-V
K.3.401
RISC-V application, OS, and firmware development has been slowed by the lack of "real hardware" available for developers to work with. With the rise of FPGAs in the cloud and the recent release of the OpenPiton+Ariane manycore platform on Amazon's F1 cloud FPGA platform, we propose using 1-12 core OpenPiton+Ariane processors emulated on F1 to develop RISC-V software and firmware. In this talk, we will give an accelerated tutorial on how to get started with OpenPiton+Ariane, the spec-compliant ...
2/1/20
RISC-V
Ofer Shinaar
K.3.401
We would like to present and overlay technique for RISCV, develop by WD and open sourced. This FW feature acts as a software “paging” manager. It is to be threaded with the Real-Time code and to the toolchain. Cacheable Overlay Manager RISC-V (ComRV), a technique which fits limited memory embedded devices (as IoT’s), and does not need any HW support.